Publication:

Vertical polysilicon pinch-off FET for 3D memory technology: feasibility and electrical performance

Date

2013
Proceedings Paper
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dc.contributor.authorCongedo, Gabriele
dc.contributor.authorToledano Luque, Maria
dc.contributor.authorArreghini, Antonio
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorTang, Baojun
dc.contributor.authorDegraeve, Robin
dc.contributor.authorVan Aerde, Steven
dc.contributor.authorKim, Woosik
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorVan Houdt, Jan
dc.contributor.imecauthorArreghini, Antonio
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorDegraeve, Robin
dc.contributor.imecauthorVan Aerde, Steven
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.orcidimecArreghini, Antonio::0000-0002-7493-9681
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.date.accessioned2021-10-21T07:02:05Z
dc.date.available2021-10-21T07:02:05Z
dc.date.embargo9999-12-31
dc.date.issued2013
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/22167
dc.source.beginpage159
dc.source.conferenceInternational Memory Workshop - IMW
dc.source.conferencedate26/05/2013
dc.source.conferencelocationMonterey, CA USA
dc.source.endpage162
dc.title

Vertical polysilicon pinch-off FET for 3D memory technology: feasibility and electrical performance

dc.typeProceedings paper
dspace.entity.typePublication
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