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A stochastic model for the interconnection topology of digital circuits

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dc.contributor.authorVerplaetse, P.
dc.contributor.authorStroobandt, Dirk
dc.contributor.authorVan Campenhout, Jan
dc.date.accessioned2021-10-14T18:35:09Z
dc.date.available2021-10-14T18:35:09Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5888
dc.source.beginpage938
dc.source.endpage942
dc.source.issue6
dc.source.journalIEEE Trans. on Very Large Scale Integration (VLSI) Systems
dc.source.volume9
dc.title

A stochastic model for the interconnection topology of digital circuits

dc.typeJournal article
dspace.entity.typePublication
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