Publication:
High speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compression
Date
| dc.contributor.author | Osorio, Roberto | |
| dc.contributor.author | Vanhoof, Bart | |
| dc.date.accessioned | 2021-10-15T05:57:59Z | |
| dc.date.available | 2021-10-15T05:57:59Z | |
| dc.date.issued | 2003 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/7963 | |
| dc.source.beginpage | 267 | |
| dc.source.endpage | 275 | |
| dc.source.issue | 3 | |
| dc.source.journal | Journal of VLSI Signal Processing | |
| dc.source.volume | 33 | |
| dc.title | High speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compression | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| Files | ||
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