Publication:

Buried Bitline for sub-5nm SRAM Design

Date

2020
Proceedings Paper
https://doi.org/10.1109/IEDM13553.2020.9372042
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dc.contributor.authorMathur, R.
dc.contributor.authorBhargava, M.
dc.contributor.authorAnnamalai, S.
dc.contributor.authorChong, Y. K.
dc.contributor.authorSinha, S.
dc.contributor.authorCline, B.
dc.contributor.authorKulkarni, J. P.
dc.contributor.authorSalahuddin, Shairfe Muhammad
dc.contributor.authorSchuddinck, Pieter
dc.contributor.authorRyckaert, Julien
dc.contributor.authorGupta, Anshul
dc.contributor.imecauthorSalahuddin, S.
dc.contributor.imecauthorSchuddinck, P.
dc.contributor.imecauthorRyckaert, J.
dc.contributor.imecauthorGupta, A.
dc.contributor.imecauthorSalahuddin, Shairfe Muhammad
dc.contributor.imecauthorSchuddinck, Pieter
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorGupta, Anshul
dc.contributor.orcidimecSalahuddin, Shairfe Muhammad::0000-0002-6483-8430
dc.date.accessioned2021-12-06T10:24:15Z
dc.date.available2021-12-06T02:06:50Z
dc.date.available2021-12-06T10:24:15Z
dc.date.issued2020
dc.identifier.doi10.1109/IEDM13553.2020.9372042
dc.identifier.eisbn978-1-7281-8888-1
dc.identifier.issn2380-9248
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/38565
dc.publisherIEEE
dc.source.conferenceIEEE International Electron Devices Meeting (IEDM)
dc.source.conferencedateDEC 12-18, 2020
dc.source.conferencelocationSan Francisco, CA, USA
dc.source.journalna
dc.source.numberofpages4
dc.title

Buried Bitline for sub-5nm SRAM Design

dc.typeProceedings paper
dspace.entity.typePublication
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