Towards SoCs leveraging 200nm wafer-to-wafer interconnection pitch

Abstract

This paper highlights the advantages of 3D System-on-Chip (SoC) but also shows that system-technology co-optimization (STCO) will be required for system-level benefits. A physical design study was performed evaluating the design feasibility when multi-threading CPUs. The study shows that 250nm 3D pitches can enable this performance benefit without area penalties. To achieve this, two high density 3D interconnect technology enablers are described. For wafer-to-wafer Cu-SiCN hybrid bonding technology the challenges are outlined to enable scaling down the interconnect pitch from 300nm down to 200nm. Nano Through-Silicon Via (nTSV) technology enables fine-pitch 210nm and 120nm vertical connections between the frontside and backside of a wafer through extreme wafer thinning and overlay control in backside lithography.