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Architectural exploration and optimization for counter based hardware address generation

Date

1997
Proceedings Paper
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dc.contributor.authorMiranda, Miguel
dc.contributor.authorKaspar, Martin
dc.contributor.authorCatthoor, Francky
dc.contributor.authorDe Man, Hugo
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorDe Man, Hugo
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2021-09-30T09:18:33Z
dc.date.available2021-09-30T09:18:33Z
dc.date.issued1997
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/2027
dc.source.beginpage293
dc.source.conferenceEuropean Design & Test Conference - ED&TC 97
dc.source.conferencedate17/03/1997
dc.source.conferencelocationParis France
dc.source.endpage298
dc.title

Architectural exploration and optimization for counter based hardware address generation

dc.typeProceedings paper
dspace.entity.typePublication
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