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A 86MHz-12GHz digital-intensive, phase-modulated fractional-N PLL, using a 15pJ/shot 5ps TDC in 40nm digital CMOS

Date

2010
Proceedings Paper
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dc.contributor.authorBorremans, Jonathan
dc.contributor.authorVengattaramane, Kameswaran
dc.contributor.authorGiannini, Vito
dc.contributor.authorCraninckx, Jan
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.accessioned2021-10-18T15:23:54Z
dc.date.available2021-10-18T15:23:54Z
dc.date.embargo9999-12-31
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16777
dc.source.beginpage480
dc.source.conferenceIEEE International Solid-State Circuits Conference - ISSCC
dc.source.conferencedate7/02/2010
dc.source.conferencelocationSan Francisco, CA USA
dc.source.endpage481
dc.title

A 86MHz-12GHz digital-intensive, phase-modulated fractional-N PLL, using a 15pJ/shot 5ps TDC in 40nm digital CMOS

dc.typeProceedings paper
dspace.entity.typePublication
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