Publication:

COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications

Date

2023
Journal article
https://doi.org/10.1016/j.sysarc.2023.103022
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dc.contributor.authorMarinelli, Tommaso
dc.contributor.authorPerez, Jose Ignacio Gomez
dc.contributor.authorTenllado, Christian
dc.contributor.authorCatthoor, Francky
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2024-03-18T12:28:24Z
dc.date.available2024-02-11T17:06:51Z
dc.date.available2024-03-18T12:28:24Z
dc.date.embargo2023-12-31
dc.date.issued2023
dc.description.wosFundingTextThis work has been supported by grant PID2021-123041OB-I00 funded by MCIN/AEI/10.13039/501100011033 (Spanish Ministry of Science and Innovation) and by "ERDF A way of making Europe" (European Regional Development Fund) , and by the CM (Community of Madrid , Spain) under grant S2018/TCS-4423.
dc.identifier.doi10.1016/j.sysarc.2023.103022
dc.identifier.issn1383-7621
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/43531
dc.publisherELSEVIER
dc.source.beginpageArt. 103022
dc.source.endpageN/A
dc.source.issueDecember
dc.source.journalJOURNAL OF SYSTEMS ARCHITECTURE
dc.source.numberofpages11
dc.source.volume145
dc.title

COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications

dc.typeJournal article
dspace.entity.typePublication
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