Publication:
Influence of gate length on ESD-performance for deep submicron CMOS technology
Date
| dc.contributor.author | Bock, Karlheinz | |
| dc.contributor.author | Keppens, Bart | |
| dc.contributor.author | De Heyn, Vincent | |
| dc.contributor.author | Groeseneken, Guido | |
| dc.contributor.author | Ching, L. Y. | |
| dc.contributor.author | Naem, Abdalla | |
| dc.contributor.imecauthor | De Heyn, Vincent | |
| dc.contributor.imecauthor | Groeseneken, Guido | |
| dc.date.accessioned | 2021-10-14T16:37:55Z | |
| dc.date.available | 2021-10-14T16:37:55Z | |
| dc.date.issued | 2001 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/5074 | |
| dc.source.beginpage | 375 | |
| dc.source.endpage | 383 | |
| dc.source.issue | 3 | |
| dc.source.journal | Microelectronics Reliability | |
| dc.source.volume | 41 | |
| dc.title | Influence of gate length on ESD-performance for deep submicron CMOS technology | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| Files | ||
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