Positive Bias Temperature Instability (PBTI) in n-and p-channel polysilicon thin-film transistors (TFTs) for high-voltage applications

Abstract

Positive Bias Temperature Instability (PBTI) degradation is studied at stress voltages of 25–45 V and at room and elevated temperatures in low-temperature polysilicon (LTPS) Thin Film Transistors (TFTs). Positive threshold voltage shifts observed in both n- and p-TFTs cannot be explained by the typically-reported amphoteric Si dangling bonds. Two apparently-independent and counteracting PBTI degradation mechanisms (components) are identified in similarly-degrading n- and p-TFTs. The generation component is seen to be driven by gate bias and at most weakly dependent on temperature 𝑇, unlike the strongly 𝑇-dependent counteracting “anomalous” annihilation component. The time kinetics of both components are proposed.