In-depth DC characterization of asymmetric vertical nanowire Accumulation-Mode junctionless GAA pMOSFETs on SOI from 300 K to 400 K

Abstract

In this article, we present an in-depth investigation of the direct current (DC) characteristics of asymmetric vertical nanowire (VNW) accumulation-mode junctionless (JL) gate-all-around (GAA) pMOSFETs fabricated on silicon-on-insulator (SOI) substrates. Measurements were performed over a temperature range from 300 K to 400 K in both linear and saturation regimes. Our results reveal significant temperature and polarization-dependent behaviors. It has been demonstrated that the nanowire diameter impacts the DC performance. A nanowire diameter larger than 20 nm leads to a significant increase in off-state leakage current and a higher on-state drive current compared to smaller diameters. Although a larger diameter improves the on-state current, it degrades the subthreshold swing (SS), indicating weaker electrostatic control. Furthermore, using the top electrode as either the drain (forward operation mode) or the source (reverse operation mode) significantly affects device performance due to their asymmetric architecture. In the forward mode, a higher off-state leakage current is observed, while in the reverse mode, the on-state saturation current is higher. This asymmetry may be attributed to asymmetric access resistances ( ). From high-temperature measurements, using different series-resistance-free parameter-extraction (Y-function-based) methodologies, it is observed that the series resistance of the devices remains unchanged, and the low-field mobility is mainly limited by Coulomb scattering. This study provides a better understanding of the behavior and performance of VNW accumulation-mode JL GAA pMOSFETs and paves the way for further optimization.