Publication:
200 MBit/s 4-symbol arithmetic encoder architecture for embedded zero tree-based compression
Date
| dc.contributor.author | Osorio, Roberto | |
| dc.contributor.author | Vanhoof, Bart | |
| dc.date.accessioned | 2021-10-14T17:32:55Z | |
| dc.date.available | 2021-10-14T17:32:55Z | |
| dc.date.issued | 2001 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/5557 | |
| dc.source.beginpage | 397 | |
| dc.source.conference | Proceedings IEEE workshop on Signal Processing Systems - SIPS | |
| dc.source.conferencedate | 26/09/2001 | |
| dc.source.conferencelocation | Antwerpen | |
| dc.source.endpage | 405 | |
| dc.title | 200 MBit/s 4-symbol arithmetic encoder architecture for embedded zero tree-based compression | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
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