Accurate off-current evaluation by parasitic capacitance extraction in capacitor-less DRAM cells

Abstract

We enable the accurate extraction of the off-current (Ioff) values in capacitor-less 2-transistor (2T0C) DRAM cells by developing two experimental methods for assessing the parasitic capacitance (Cpara). We thus consider the total storage node capacitance (Ctot = CoxRtr + Cpara) instead of the conventional gate capacitance of the read transistor (CoxRtr) for the extraction of Ioff. The application of these methods to our fabricated IGZO-based 2T0C devices reveals that the correction factor Ctot/CoxRtr can be more than ten for scaled devices. This is corroborated with simulations for parasitic extraction and subthreshold leakage analysis. Even after applying this correction, our IGZO thin film transistors achieve Ioff/W < 5 × 10-20 off A/µm in 2T0C devices.