Publication:
Nanometer-scale SiGe lateral recess metrology in CFET structures using micro-spot X-ray fluorescence
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| dc.contributor.author | Kim, Jenna | |
| dc.contributor.author | Bogdanowicz, Janusz | |
| dc.contributor.author | Mingardi, Andrea | |
| dc.contributor.author | Puttarame Gowda, Pallavi | |
| dc.contributor.author | Stiers, Karen | |
| dc.contributor.author | Murakami, S. | |
| dc.contributor.author | Kuhn, M. | |
| dc.contributor.author | Yang, Hongcheon | |
| dc.contributor.author | Moussa, Alain | |
| dc.contributor.author | Kim, Min-Soo | |
| dc.contributor.author | Biesemans, Serge | |
| dc.contributor.author | Leray, Philippe | |
| dc.contributor.author | Charley, Anne-Laure | |
| dc.date.accessioned | 2026-09-21T10:15:17Z | |
| dc.date.available | 2026-09-21T10:15:17Z | |
| dc.date.createdwos | 2026 | |
| dc.date.issued | 2026 | |
| dc.description.abstract | Complementary FET (CFET) architectures stack nMOS and pMOS devices vertically, creating buried features that challenge conventional metrology. A critical module is the selective SiGe lateral recess, which defines the gate length and inner-spacer width and strongly impacts device performance. TEM and OCD provide valuable insight but face limitations in throughput, scalability, or sensitivity for recessed structures. We demonstrate micro-spot X-ray fluorescence (µXRF) as a non-destructive, wafer-scale method to quantify SiGe recess depth in device-relevant CFETs. Normalizing the Ge Kα signal using an on-wafer Si/SiGe reference stack isolates the lateral geometry; the normalized signal correlates strongly with top-view SEM dimensions and TEM-derived SiGe lengths (R2 ≈ 0.996). Applying this calibration across 495 dies per wafer reveals clear radial non-uniformity of the lateral recess. Repeatability and error propagation show a calibration-limited 3σ depth-resolution floor of ∼1.4 nm, with intrinsic µXRF sensitivity < 1 nm at dwell times of about one minute—indicating strong potential for future inline monitoring. | |
| dc.description.wosFundingText | This work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union's Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit https://www.nanoic-project.eu. | |
| dc.identifier.doi | 10.1117/12.3087689 | |
| dc.identifier.eissn | 1996-756X | |
| dc.identifier.isbn | 978-1-5106-9908-3 | |
| dc.identifier.issn | 0277-786X | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/60426 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | SPIE-INT SOC OPTICAL ENGINEERING | |
| dc.relation.ispartofseries | Proceedings of SPIE | |
| dc.source.beginpage | 139810Z | |
| dc.source.conference | Metrology, Inspection, and Process Control XL | |
| dc.source.conferencedate | 2026-02-22 | |
| dc.source.conferencelocation | San Jose | |
| dc.source.journal | METROLOGY, INSPECTION, AND PROCESS CONTROL XL, PT 1 | |
| dc.source.numberofpages | 8 | |
| dc.title | Nanometer-scale SiGe lateral recess metrology in CFET structures using micro-spot X-ray fluorescence | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-07-14 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-09-07 | |
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