2025 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, IIRW
Abstract
Time-Dependent Dielectric Breakdown (TDDB) is a key reliability challenge in advanced CMOS technologies, particularly under low thermal budget (LT) constraints required for Complementary FET's (CFET's) and Sequential 3D (Seq3D) integration. We study the impact of prolonged LT high-k postdeposition anneals (PDA) on the TDDB reliability of pMOS gate stacks and defect activation energy distributions. To decouple the effect of dielectric precursor density from changes in EOT and Vfb, we propose benchmarking methods for gate stack comparison. Results show a saturation of the time-to-breakdown (tbd) improvement with prolonged anneal performed at 450°C. To investigate the distribution of precursor defect activation energies, we employ our recently proposed Markov model, reformulating the voltage dependence of the defect generation in terms of the oxide electric field. The study of the defect generation efficiency in each gate stack suggests different types of carrier transport having different defect generation efficiencies.