Radiation Hardening by Design Concepts for 7-nm FinFET Technologies

Abstract

For ultra deep sub-micron technologies, charge sharing affects areas beyond the standard cell dimensions. Scaling up cells to ensure no charge sharing occurs inside therefore would have a major negative impact on area efficiency. We propose a D-flip-flop based on the principles of multi-bit flip-flops with integrated majority voters for the Triple Modular Redundancy (TMR) scheme, where the internal triplicated elements respect the critical spacing requirement and the cell can be used as a intrinsic rad-hard cell that requires no additional radiation mitigation on system level. We discuss the design trade-offs and compare the performance parameters of single- and multi-bit D-flip-flops from the standard library with the designed 2-bit TMR and 1-bit (Dual Interlocked Cell-based (DICE) DFFs.