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Physical design solutions to tackle FEOL/BEOL degradation in gate-level monolithic 3D ICs

Date

2016
Proceedings Paper
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dc.contributor.authorKu, Bon Woong
dc.contributor.authorDebacker, Peter
dc.contributor.authorMilojevic, Dragomir
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorVerkest, Diederik
dc.contributor.authorThean, Aaron
dc.contributor.authorLim, Sung Kyu
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorMilojevic, Dragomir
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.accessioned2021-10-23T11:55:23Z
dc.date.available2021-10-23T11:55:23Z
dc.date.issued2016
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26853
dc.identifier.urlhttp://dl.acm.org/citation.cfm?id=2934622
dc.source.beginpage76
dc.source.conferenceProceedings of the International Symposium on Low Power Electronics and Design - ISLPED
dc.source.conferencedate8/08/2016
dc.source.conferencelocationSan Fransisco, CA USA
dc.source.endpage81
dc.title

Physical design solutions to tackle FEOL/BEOL degradation in gate-level monolithic 3D ICs

dc.typeProceedings paper
dspace.entity.typePublication
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