Publication:

A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range

Date

2023
Proceedings Paper
https://doi.org/10.1109/ESSCIRC59616.2023.10268699
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dc.contributor.authorHsu, Wen-Yang
dc.contributor.authorAymerich, Joan
dc.contributor.authorYang, Xiaolin
dc.contributor.authorSawigun, Chutham
dc.contributor.authorCoppejans, Philippe
dc.contributor.authorMora Lopez, Carolina
dc.contributor.imecauthorHsu, Wen-Yang
dc.contributor.imecauthorAymerich, Joan
dc.contributor.imecauthorYang, Xiaolin
dc.contributor.imecauthorSawigun, Chutham
dc.contributor.imecauthorCoppejans, Philippe
dc.contributor.imecauthorMora Lopez, Carolina
dc.contributor.orcidimecHsu, Wen-Yang::0000-0002-8706-0553
dc.contributor.orcidimecYang, Xiaolin::0000-0001-9900-528X
dc.contributor.orcidimecSawigun, Chutham::0000-0001-7179-0343
dc.contributor.orcidimecMora Lopez, Carolina::0000-0003-4200-0001
dc.date.accessioned2023-12-18T09:30:50Z
dc.date.available2023-11-12T17:45:35Z
dc.date.available2023-12-18T09:30:50Z
dc.date.issued2023
dc.description.wosFundingTextThe authors thank Andrea Lodi for the PCB design support. This research was partially supported by the NIH grant 1U01NS115587 (Neuropixels NXT).
dc.identifier.doi10.1109/ESSCIRC59616.2023.10268699
dc.identifier.eisbn979-8-3503-0420-6
dc.identifier.issn1930-8833
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/43133
dc.publisherIEEE
dc.source.beginpage253
dc.source.conferenceIEEE 49th European Solid-State Circuits Conference (ESSCIRC)
dc.source.conferencedateSEP 11-14, 2023
dc.source.conferencelocationLisbon
dc.source.endpage256
dc.source.journalna
dc.source.numberofpages4
dc.title

A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range

dc.typeProceedings paper
dspace.entity.typePublication
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