Publication:

Forksheet Field-Effect Transistors for Area Scaling and Gate-Drain Capacitance Reduction in Nanosheet-based CMOS Technologies

Date

2024
Proceedings Paper
https://doi.org/10.1109/EDTM58488.2024.10511640
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cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0001-5490-0416
cris.virtual.orcid0000-0002-3392-6892
cris.virtualsource.department9f04b13f-f81c-4d48-a5bd-0b2cb5210392
cris.virtualsource.department49b2e4a0-e3c7-4524-b945-f94059646804
cris.virtualsource.orcid9f04b13f-f81c-4d48-a5bd-0b2cb5210392
cris.virtualsource.orcid49b2e4a0-e3c7-4524-b945-f94059646804
dc.contributor.authorMertens, Hans
dc.contributor.authorHoriguchi, Naoto
dc.contributor.imecauthorMertens, H.
dc.contributor.imecauthorHoriguchi, N.
dc.date.accessioned2024-09-14T17:21:07Z
dc.date.available2024-09-14T17:21:07Z
dc.date.issued2024
dc.identifier.doi10.1109/EDTM58488.2024.10511640
dc.identifier.eisbn979-8-3503-7152-9
dc.identifier.isbn979-8-3503-8308-9
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44482
dc.publisherIEEE
dc.source.beginpage756
dc.source.conference8th Electron Devices Technology & Manufacturing Conference (EDTM)
dc.source.conferencedate2024-03-03
dc.source.conferencelocationBangalore
dc.source.endpage758
dc.source.numberofpages3
dc.title

Forksheet Field-Effect Transistors for Area Scaling and Gate-Drain Capacitance Reduction in Nanosheet-based CMOS Technologies

dc.typeProceedings paper
dspace.entity.typePublication
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