Publication:

Towards efficient ESD protection strategies for advanced 3D systems-on-chip

Date

2024
Editorial Material
https://doi.org/10.1038/s44287-024-00071-4
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cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0002-3623-1842
cris.virtual.orcid0000-0002-8803-8374
cris.virtualsource.department894d712a-328b-43e9-8331-871ceac6a4e6
cris.virtualsource.departmentc4a4eb19-085c-45ab-b66e-8465e2ed7660
cris.virtualsource.orcid894d712a-328b-43e9-8331-871ceac6a4e6
cris.virtualsource.orcidc4a4eb19-085c-45ab-b66e-8465e2ed7660
dc.contributor.authorLin, Shih-Hsiang (Shane)
dc.contributor.authorSimicic, Marko
dc.contributor.authorPantano, Nicolas
dc.date.accessioned2026-06-15T14:13:23Z
dc.date.available2026-06-15T14:13:23Z
dc.date.createdwos2025-12-03
dc.date.issued2024
dc.description.abstract2.5D/3D technologies require designers to reduce electrostatic discharge (ESD) protection of the internal I/O interfaces. To avoid over-design of ESD protection, designers require a more fundamental understanding of the ESD events that occur at this level. Here we present insights, practical guidelines and research directions for circuit designers and suppliers of bonding tools.
dc.identifier.doi10.1038/s44287-024-00071-4
dc.identifier.issn2948-1201
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59719
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherSPRINGERNATURE
dc.source.beginpage429
dc.source.endpage431
dc.source.issue7
dc.source.journalNATURE REVIEWS ELECTRICAL ENGINEERING
dc.source.numberofpages3
dc.source.volume1
dc.title

Towards efficient ESD protection strategies for advanced 3D systems-on-chip

dc.typeEditorial material
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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