Optical Overlay Metrology Challenges in Next-Gen Semiconductor Nodes

Abstract

The transition to next-generation semiconductor nodes is reshaping overlay metrology requirements, driven by increasing complexity in advanced logic, DRAM, 3D NAND devices, as well as Wafer-to-Wafer (W2W) and Die-to-Wafer (D2W) bonding applications. These architectures demand precise alignment across multiple layers, materials, and bonding interfaces. Key challenges include tighter On Product Overlay (OPO) specifications, thicker topographies, the use of exotic hard-mask materials, and reduced scribe line real estate. Addressing these challenges requires overlay metrology systems with specialized architectures and capabilities, including advanced wafer handling, extended wavelength support, and compatibility with diverse target designs. Imaging-Based Overlay (IBO) platforms now accommodate small-pitch targets for improved device-level representation, while Scatterometry-Based Overlay (SCOL) systems enhance measurement accuracy through wavelength-specific pupil imaging. For W2W bonding, infrared-based metrology and integrated feedback/feedforward control are being developed to manage overlay across thick, bowed substrates. D2W applications introduce spatially distributed overlay marks, necessitating large field-of-view. In specialty segments such as power and glass-based devices, metrology tools must support transparent wafer handling, variable thicknesses and bow, and multiple wafer diameters across substrates like silicon carbide (SiC), gallium nitride (GaN), and glass. These requirements are met through modular tool platforms offering Short Wave Infrared (SWIR) imaging, flexible target support, and high-throughput performance. This paper provides a comprehensive overview of these technologies and their role in enabling accurate, scalable overlay metrology across diverse semiconductor manufacturing environments.