Publication:

Semi-Damascene FSAV: Via CD and Overlay Process Window Analysis

Date

2026
Journal article
https://doi.org/10.1109/tsm.2026.3659882
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dc.contributor.authorHermans, Yannick
dc.contributor.authorMarti, Giulio
dc.contributor.authorDelie, Gilles
dc.contributor.authorMurdoch, Gayle
dc.contributor.authorMingardi, Andrea
dc.contributor.authorHalder, Sandip
dc.contributor.authorWu, Chen
dc.contributor.authorPark, Seongho
dc.contributor.authorTokei, Zsolt
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dc.date.accessioned2026-09-14T14:14:01Z
dc.date.available2026-09-14T14:14:01Z
dc.date.createdwos2026
dc.date.issued2026
dc.description.abstractThis study investigates the metal pitch 18 (MP18) via critical dimension (CD) and overlay process window (PW) for a two-metal-layer Ru semi-damascene integration scheme with a fully self-aligned via (FSAV) approach. The via CD and overlay PW was experimentally assessed from electrical tests probing the Kelvin via resistance yield and via-to-line leakage yield under a changing via CD and via y-overlay. Results show that >80% yield can be obtained for a 26.3 +/−2.0 nm via litho CD and a +/−4 nm via y-overlay PW for FSAV semi-damascene.
dc.identifier.doi10.1109/tsm.2026.3659882
dc.identifier.eissn1558-2345
dc.identifier.issn0894-6507
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60367
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.relation.ispartofseriesIEEE Transactions on Semiconductor Manufacturing
dc.source.beginpage369
dc.source.endpage371
dc.source.issue2
dc.source.journalIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
dc.source.numberofpages3
dc.source.volume39
dc.title

Semi-Damascene FSAV: Via CD and Overlay Process Window Analysis

dc.typeJournal article
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-09-07
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