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Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation

 
dc.contributor.authorLee, Jaehyun
dc.contributor.authorAsenov, Plamen
dc.contributor.authorRhyner, Reto
dc.contributor.authorKao, Ethan
dc.contributor.authorAmoroso, Salvatore M.
dc.contributor.authorBrown, Andrew R.
dc.contributor.authorLin, Xi-Wei
dc.contributor.authorMoroz, Victor
dc.contributor.imecauthorKao, Ethan
dc.contributor.orcidimecKao, Ethan::0000-0003-1662-585X
dc.date.accessioned2024-08-22T12:03:00Z
dc.date.available2024-03-14T18:00:41Z
dc.date.available2024-08-22T12:03:00Z
dc.date.issued2024
dc.identifier.doi10.1109/TED.2024.3357615
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/43669
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage1893
dc.source.endpage1899
dc.source.issue3
dc.source.journalIEEE TRANSACTIONS ON ELECTRON DEVICES
dc.source.numberofpages7
dc.source.volume71
dc.subject.keywordsRETENTION TIME DISTRIBUTION
dc.subject.keywordsCHALLENGES
dc.subject.keywordsISSUES
dc.title

Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation

dc.typeJournal article
dspace.entity.typePublication
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