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ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable Matrix

Date

2003
Proceedings Paper
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dc.contributor.authorMei, Bingfeng
dc.contributor.authorVernalde, Serge
dc.contributor.authorVerkest, Diederik
dc.contributor.authorDe Man, Hugo
dc.contributor.authorLauwereins, Rudy
dc.contributor.imecauthorVernalde, Serge
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorDe Man, Hugo
dc.contributor.imecauthorLauwereins, Rudy
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecLauwereins, Rudy::0000-0002-3861-0168
dc.date.accessioned2021-10-15T05:41:11Z
dc.date.available2021-10-15T05:41:11Z
dc.date.embargo9999-12-31
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7886
dc.source.beginpage61
dc.source.conference13th International Conference on Field-Programmable Logic and Applications
dc.source.conferencedate1/09/2003
dc.source.conferencelocationLisboa Portugal
dc.source.endpage70
dc.title

ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable Matrix

dc.typeProceedings paper
dspace.entity.typePublication
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