Publication:

Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies

Date

2023
Proceedings Paper
https://doi.org/10.1109/VTS56346.2023.10139932
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dc.contributor.authorPavanello, Fabio
dc.contributor.authorVatajelu, Elena Ioana
dc.contributor.authorBosio, Alberto
dc.contributor.authorVan Vaerenbergh, Thomas
dc.contributor.authorBienstman, Peter
dc.contributor.authorCharbonnier, Benoit
dc.contributor.authorCarpegna, Alessio
dc.contributor.authorDi Carlo, Stefano
dc.contributor.authorSavino, Alessandro
dc.contributor.imecauthorBienstman, Peter
dc.contributor.orcidimecBienstman, Peter::0000-0001-6259-464X
dc.date.accessioned2024-03-21T10:41:52Z
dc.date.available2023-07-24T17:10:23Z
dc.date.available2024-03-21T10:41:52Z
dc.date.embargo2023-04-30
dc.date.issued2023
dc.description.wosFundingTextThis project has received funding from the European Union's Horizon Europe research and innovation programme under grant agreement No. 101070238. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union. Neither the European Union nor the granting authority can be held responsible for them. It was also partially supported by the ANR within the EMINENT Project ANR-19-CE24-0001
dc.identifier.doi10.1109/VTS56346.2023.10139932
dc.identifier.eisbn979-8-3503-4630-5
dc.identifier.issn1093-0167
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/42190
dc.publisherIEEE COMPUTER SOC
dc.source.conference41st IEEE VLSI Test Symposium (VTS)
dc.source.conferencedateAPR 24-26, 2023
dc.source.conferencelocationSan Diego
dc.source.journalN/A
dc.source.numberofpages10
dc.subject.keywordsNEURAL-NETWORKS
dc.subject.keywordsPROCESSOR
dc.subject.keywordsNEURONS
dc.subject.keywordsMODEL
dc.title

Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies

dc.typeProceedings paper
dspace.entity.typePublication
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