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Gate Side Injection Operating Mode for 3D NAND Flash Memories

 
dc.contributor.authorBreuil, Laurent
dc.contributor.authorIzmailov, Roman
dc.contributor.authorPopovici, Mihaela Ioana
dc.contributor.authorStiers, Jimmy
dc.contributor.authorArreghini, Antonio
dc.contributor.authorRamesh, S
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorVan Houdt, Jan
dc.contributor.authorRosmeulen, Maarten
dc.contributor.imecauthorBreuil, L.
dc.contributor.imecauthorIzmailov, R.
dc.contributor.imecauthorPopovici, M.
dc.contributor.imecauthorStiers, J.
dc.contributor.imecauthorArreghini, A.
dc.contributor.imecauthorRamesh, S.
dc.contributor.imecauthorVan den Bosch, G.
dc.contributor.imecauthorVan Houdt, J.
dc.contributor.imecauthorRosmeulen, M.
dc.date.accessioned2024-07-12T18:43:09Z
dc.date.available2024-07-12T18:43:09Z
dc.date.issued2024
dc.description.wosFundingTextThis work has been funded by imec's Industrial Affiliation Program on Storage Memory devices.
dc.identifier.doi10.1109/IMW59701.2024.10536976
dc.identifier.eisbn979-8-3503-0652-1
dc.identifier.issn2330-7978
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44151
dc.publisherIEEE
dc.source.conferenceInternational Memory Workshop (IMW)
dc.source.conferencedate2024-05-12
dc.source.conferencelocationSeoul
dc.source.numberofpages4
dc.title

Gate Side Injection Operating Mode for 3D NAND Flash Memories

dc.typeProceedings paper
dspace.entity.typePublication
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