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Si-passivated Ge nMOS gate stack with low DIT and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal
Publication:
Si-passivated Ge nMOS gate stack with low DIT and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal
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Date
2016
Proceedings Paper
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Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Arimura, Hiroaki
;
Cott, Daire
;
Loo, Roger
;
Vanherle, Wendy
;
Xie, Qi
;
Tang, Fu
;
Jiang, Xiaoqiang
;
Franco, Jacopo
;
Sioncke, Sonja
;
Ragnarsson, Lars-Ake
;
Chiu, Eddie
;
Lu, Xiaowan
;
Geypen, Jef
;
Bender, Hugo
;
Maes, Jan
;
Givens, Michael
;
Sibaja-Hernandez, Arturo
;
Wostyn, Kurt
;
Boccardi, Guillaume
;
Mitard, Jerome
;
Collaert, Nadine
;
Mocuta, Dan
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1923
since deposited on 2021-10-23
Acq. date: 2025-12-10
Citations
Metrics
Views
1923
since deposited on 2021-10-23
Acq. date: 2025-12-10
Citations