Bias temperature instability in 22nm FDSOI transistors at cryogenic temperatures

Abstract

The realization of practical, large-scale quantum computers requires the optimization of classical electronics for cryogenic operation to solve the interconnect bottleneck between quantum processors and control electronics. Devices from Fully-depleted Silicon-on-insulator (FDSOI) technology nodes are ideal for cryogenic operation due to the possibility of tuning the threshold voltage through the back-gate and reducing power consumption. However, they must be assessed in terms of not just their performance but also their reliability at conditions of interest. In this study, we present the Bias Temperature Instability (BTI) characteristics of commercial 22 nm FDSOI transistors optimized for low-power applications at temperatures ranging from 300 K down to 4 K, focusing on the impact of stress time and gate overdrive voltage. We observe that BTI remains active in both pMOS and nMOS at 4K with weak dependencies on stress magnitude and duration. Crucially, recovery from threshold voltage shifts is also slowed down at cryogenic temperatures.