Hybrid copper dielectric direct bonding of 200mm CMOS wafers with five metal levels: morphologic, electrical and reliability characterization

Abstract

For the first-time imec reports wafer level electrical data and reliability testing results for 200-mm wafer to wafer hybrid copper to dielectric aligned bonding. In this work, bonding was performed on short loop wafers which consist of five backend of line (BEOL) metal levels. Silicon carbon nitride (SiCN) was chosen as the dielectric layer to be used in the hybrid bonding process reported in this paper. The bonding interface and processed metal levels morphologic quality was evaluated through scanning acoustic microscopic imaging and by focused ion beam imaging. To evaluate the electrical performance of 10 μm pitch bonded test structures with copper bonding pads of 2 μm by 2 μm size, resistance structures, kelvin structures, and daisy chains were used. The fabricated daisy chains have up to 2500 copper pads per chain and are available in different geometries, linear and interwoven. Both kelvin structures and daisy chains are available as well in a configuration where the vias between metal level are staggered and non-staggered. To move towards a technology qualification of the fabricated test structures, stress driven qualification of the fabricated test structures was performed. The performed tests were high temperature stress testing and temperature cycling testing.