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Challenges and opportunities of vertical FET devices using 3D circuit design layouts
Publication:
Challenges and opportunities of vertical FET devices using 3D circuit design layouts
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Date
2016
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Veloso, Anabela
;
Huynh Bao, Trong
;
Rosseel, Erik
;
Paraschiv, Vasile
;
Devriendt, Katia
;
Vecchio, Emma
;
Delvaux, Christie
;
Chan, BT
;
Ercken, Monique
;
Tao, Zheng
;
Li, Waikin
;
Altamirano Sanchez, Efrain
;
Versluijs, Janko
;
Brus, Stephan
;
Matagne, Philippe
;
Waldron, Niamh
;
Ryckaert, Julien
;
Mocuta, Dan
;
Collaert, Nadine
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2007
since deposited on 2021-10-23
2
last month
Acq. date: 2026-01-10
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Views
2007
since deposited on 2021-10-23
2
last month
Acq. date: 2026-01-10
Citations