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Towards the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture

Date

2007-05
Proceedings Paper
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dc.contributor.authorLopez, Sebastian
dc.contributor.authorKanstein, Andreas
dc.contributor.authorLopez, J. F.
dc.contributor.authorBerekovic, Mladen
dc.contributor.authorSarmiento, R.
dc.contributor.authorMignolet, Jean-Yves
dc.date.accessioned2021-10-16T17:38:19Z
dc.date.available2021-10-16T17:38:19Z
dc.date.embargo9999-12-31
dc.date.issued2007-05
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/12513
dc.source.beginpage65900A
dc.source.conferenceVLSI Circuits and Systems III
dc.source.conferencedate2/05/2007
dc.source.conferencelocationMaspalomas Spain
dc.title

Towards the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture

dc.typeProceedings paper
dspace.entity.typePublication
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