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The impact of layout on stress-enhanced transistor performance
Publication:
The impact of layout on stress-enhanced transistor performance
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Date
2005
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Moroz, Victor
;
Eneman, Geert
;
Verheyen, Peter
;
Nouri, Faran
;
Washington, Lori
;
Smith, Lee
;
Jurczak, Gosia
;
Pramanik, Dipu
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1895
since deposited on 2021-10-16
1
last month
Acq. date: 2025-12-09
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Metrics
Views
1895
since deposited on 2021-10-16
1
last month
Acq. date: 2025-12-09
Citations