Publication:

System-level ESD protection of high-voltage tolerant IC pins – A case study with nLDMOS SCR

Date

2011
Proceedings Paper
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dc.contributor.authorScholz, Mirko
dc.contributor.authorThijs, Steven
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorGriffoni, Alessio
dc.contributor.authorLinten, Dimitri
dc.contributor.authorSawada, Masanori
dc.contributor.authorVandersteen, Gerd
dc.contributor.authorGroeseneken, Guido
dc.contributor.imecauthorThijs, Steven
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorVandersteen, Gerd
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecThijs, Steven::0000-0003-2889-8345
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecChen, Shih-Hung::0000-0002-6481-2951
dc.contributor.orcidimecGroeseneken, Guido::0000-0003-3763-2098
dc.date.accessioned2021-10-19T18:32:09Z
dc.date.available2021-10-19T18:32:09Z
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19743
dc.source.conference21st RCJ Reliability Symposium
dc.source.conferencedate1/11/2011
dc.source.conferencelocationTokyo Japan
dc.title

System-level ESD protection of high-voltage tolerant IC pins – A case study with nLDMOS SCR

dc.typeProceedings paper
dspace.entity.typePublication
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