STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance

dc.contributor.author	Appeltans, Raf
dc.contributor.author	Cosemans, Stefan
dc.contributor.author	Raghavan, Praveen
dc.contributor.author	Verkest, Diederik
dc.contributor.author	Van der Perre, Liesbet
dc.contributor.author	Dehaene, Wim
dc.contributor.imecauthor	Appeltans, Raf
dc.contributor.imecauthor	Cosemans, Stefan
dc.contributor.imecauthor	Verkest, Diederik
dc.contributor.imecauthor	Dehaene, Wim
dc.contributor.orcidimec	Verkest, Diederik::0000-0001-6567-2746
dc.date.accessioned	2021-10-22T18:30:28Z
dc.date.available	2021-10-22T18:30:28Z
dc.date.issued	2015
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/24937
dc.identifier.url	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7304355
dc.source.beginpage	1
dc.source.conference	IEEE Non-Volatile Memory System and Applications Symposium - NVMSA
dc.source.conferencedate	19/08/2015
dc.source.conferencelocation	Hong Kong Hong Kong
dc.source.endpage	6
dc.title	STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance
dc.type	Proceedings paper
dspace.entity.type	Publication
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