Influence of Dielectric Materials and Via Geometry on the Thermomechanical Behavior of Silicon Through Interconnects

Abstract

During manufacturing and subsequent service loads, silicon-through via interconnects are subjected to thermal stresses and strains. This effect is mainly caused by the high Coefficient of Thermal Expansion (CTE) mismatch between the copper via and the silicon. Due to its brittle nature, moderate stresses could result in a detrimental facture of the die. Furthermore, this CTE mismatch will lead to an accumulation of irreversible strains in the copper and therefore, a failure under thermal cycling conditions can occur. In this work, Finite Element Modeling (FEM) has been used to simulate individual interconnects in order to analyze the thermal stresses and strains induced in the silicon and the copper vias during a temperature cycle. Several configurations were studied, including diameter of the via, thickness of silicon, thickness and properties of the dielectric material (SiO2, parylene) and mechanical properties of the different selections of filling material on the copper via such as copper and BCB. The results suggest that using a soft dielectric material like BCB or parylene significantly reduces the risk of silicon crack and via failure.