Publication:

Toward Fine-Grained Partitioning of Low-Level SRAM Caches for Emerging 3D-IC Designs

Date

2024
Journal article
https://doi.org/10.1109/JXCDC.2024.3468386
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dc.contributor.authorDas, Sudipta
dc.contributor.authorKumari, Bhawana
dc.contributor.authorSahoo, Siva Satyendra
dc.contributor.authorChen, Yukai
dc.contributor.authorMyers, James
dc.contributor.authorMilojevic, Dragomir
dc.contributor.authorBiswas, Dwaipayan
dc.contributor.authorRyckaert, Julien
dc.contributor.imecauthorDas, Sudipta
dc.contributor.imecauthorKumari, Bhawana
dc.contributor.imecauthorSahoo, Siva Satyendra
dc.contributor.imecauthorChen, Yukai
dc.contributor.imecauthorMyers, James
dc.contributor.imecauthorMilojevic, Dragomir
dc.contributor.imecauthorBiswas, Dwaipayan
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.orcidimecDas, Sudipta::0009-0007-2998-9827
dc.contributor.orcidimecKumari, Bhawana::0000-0002-6665-749X
dc.contributor.orcidimecSahoo, Siva Satyendra::0000-0002-2243-5350
dc.contributor.orcidimecChen, Yukai::0000-0003-3378-887X
dc.contributor.orcidimecBiswas, Dwaipayan::0000-0002-1087-3433
dc.date.accessioned2025-06-20T08:34:21Z
dc.date.available2024-10-26T16:45:25Z
dc.date.available2025-06-20T08:34:21Z
dc.date.embargo2024-10-15
dc.date.issued2024
dc.identifier.doi10.1109/JXCDC.2024.3468386
dc.identifier.issn2329-9231
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44685
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage67
dc.source.endpage74
dc.source.issueN/A
dc.source.journalIEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS
dc.source.numberofpages8
dc.source.volume10
dc.subject.keywordsPERFORMANCE
dc.subject.keywordsMEMORY
dc.title

Toward Fine-Grained Partitioning of Low-Level SRAM Caches for Emerging 3D-IC Designs

dc.typeJournal article
dspace.entity.typePublication
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