Publication:

Gate-stack engineered NBTI improvements in high-voltage logic-for-memory high-k/metal gate devices

Date

2019
Proceedings Paper
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dc.contributor.authorO'Sullivan, Barry
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorRzepa, G
dc.contributor.authorWu, Zhicheng
dc.contributor.authorDentoni Litta, Eugenio
dc.contributor.authorRichard, Olivier
dc.contributor.authorConard, Thierry
dc.contributor.authorMachkaoutsan, Vladimir
dc.contributor.authorFazan, Pierre
dc.contributor.authorKim, Cheolgyu
dc.contributor.authorFranco, Jacopo
dc.contributor.authorKaczer, Ben
dc.contributor.authorGrasser, T
dc.contributor.authorSpessot, Alessio
dc.contributor.authorLinten, Dimitri
dc.contributor.authorHoriguchi, Naoto
dc.contributor.imecauthorO'Sullivan, Barry
dc.contributor.imecauthorRitzenthaler, Romain
dc.contributor.imecauthorWu, Zhicheng
dc.contributor.imecauthorDentoni Litta, Eugenio
dc.contributor.imecauthorRichard, Olivier
dc.contributor.imecauthorConard, Thierry
dc.contributor.imecauthorMachkaoutsan, Vladimir
dc.contributor.imecauthorFazan, Pierre
dc.contributor.imecauthorFranco, Jacopo
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.orcidimecO'Sullivan, Barry::0000-0002-9036-8241
dc.contributor.orcidimecRitzenthaler, Romain::0000-0002-8615-3272
dc.contributor.orcidimecRichard, Olivier::0000-0002-3994-8021
dc.contributor.orcidimecConard, Thierry::0000-0002-4298-5851
dc.contributor.orcidimecFranco, Jacopo::0000-0002-7382-8605
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.accessioned2021-10-27T15:13:01Z
dc.date.available2021-10-27T15:13:01Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33713
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8720598
dc.source.beginpage1
dc.source.conferenceIEEE International Reliability Physics Symposium - IRPS
dc.source.conferencedate31/03/2019
dc.source.conferencelocationMonterey, CA USA
dc.source.endpage8
dc.title

Gate-stack engineered NBTI improvements in high-voltage logic-for-memory high-k/metal gate devices

dc.typeProceedings paper
dspace.entity.typePublication
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