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A 12mW 10 GHz FMCW PLL based on an integrating DAC with 28 kHz rms-frequency-error for 23 MHz/ s slope and 1.2 GHz chirp-bandwidth
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A 12mW 10 GHz FMCW PLL based on an integrating DAC with 28 kHz rms-frequency-error for 23 MHz/ s slope and 1.2 GHz chirp-bandwidth
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Date
2020
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Renukaswamy, Pratap
;
Markulic, Nereo
;
Wambacq, Piet
;
Craninckx, Jan
Journal
IEEE Journal of Solid-State Circuits
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2022
since deposited on 2021-10-29
Acq. date: 2025-12-15
Citations
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Views
2022
since deposited on 2021-10-29
Acq. date: 2025-12-15
Citations