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Standard-cell design architecture options below 5nm node: the ultimate scaling of FinFET and nanosheet

Date

2019
Proceedings Paper
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dc.contributor.authorSherazi, Yasser
dc.contributor.authorCupak, Miroslav
dc.contributor.authorWeckx, Pieter
dc.contributor.authorZografos, Odysseas
dc.contributor.authorJang, Doyoung
dc.contributor.authorDebacker, Peter
dc.contributor.authorVerkest, Diederik
dc.contributor.authorMocuta, Anda
dc.contributor.authorKim, Ryan Ryoung han
dc.contributor.authorSpessot, Alessio
dc.contributor.authorRyckaert, Julien
dc.contributor.imecauthorSherazi, Yasser
dc.contributor.imecauthorCupak, Miroslav
dc.contributor.imecauthorWeckx, Pieter
dc.contributor.imecauthorZografos, Odysseas
dc.contributor.imecauthorJang, Doyoung
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorKim, Ryan Ryoung han
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.orcidimecZografos, Odysseas::0000-0002-9998-8009
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.accessioned2021-10-27T18:07:19Z
dc.date.available2021-10-27T18:07:19Z
dc.date.embargo9999-12-31
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33987
dc.identifier.urlhttps://doi.org/10.1117/12.2514569
dc.source.beginpage1096202
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability XIII
dc.source.conferencedate24/02/2019
dc.source.conferencelocationSan Jose, CA USA
dc.title

Standard-cell design architecture options below 5nm node: the ultimate scaling of FinFET and nanosheet

dc.typeProceedings paper
dspace.entity.typePublication
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