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First-principles study of the performance degradation of 2D channel-based transistors with sub-10 nm gate lengths

Date

2015
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dc.contributor.authorLu, Augustin
dc.contributor.authorPourtois, Geoffrey
dc.contributor.authorStokbro, Kurt
dc.contributor.authorThean, Aaron
dc.contributor.authorRadu, Iuliana
dc.contributor.authorHoussa, Michel
dc.contributor.imecauthorPourtois, Geoffrey
dc.contributor.imecauthorThean, Aaron
dc.contributor.imecauthorRadu, Iuliana
dc.contributor.imecauthorHoussa, Michel
dc.contributor.orcidimecPourtois, Geoffrey::0000-0003-2597-8534
dc.contributor.orcidimecRadu, Iuliana::0000-0002-7230-7218
dc.contributor.orcidimecHoussa, Michel::0000-0003-1844-3515
dc.date.accessioned2021-10-22T20:44:19Z
dc.date.available2021-10-22T20:44:19Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25585
dc.source.conferenceIEEE Semiconductor Interface Specialists Conference - SISC
dc.source.conferencedate2/12/2015
dc.source.conferencelocationArlington, VA USA
dc.title

First-principles study of the performance degradation of 2D channel-based transistors with sub-10 nm gate lengths

dc.typeMeeting abstract
dspace.entity.typePublication
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