A 4.4 pJ/access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy

dc.contributor.author	Sharma, Vibhu
dc.contributor.author	Cosemans, Stefan
dc.contributor.author	Ashouei, Maryam
dc.contributor.author	Huisken, Jos
dc.contributor.author	Catthoor, Francky
dc.contributor.author	Dehaene, Wim
dc.contributor.imecauthor	Cosemans, Stefan
dc.contributor.imecauthor	Catthoor, Francky
dc.contributor.imecauthor	Dehaene, Wim
dc.contributor.orcidimec	Catthoor, Francky::0000-0002-3599-8515
dc.date.accessioned	2021-10-19T18:41:41Z
dc.date.available	2021-10-19T18:41:41Z
dc.date.embargo	9999-12-31
dc.date.issued	2011
dc.identifier.issn	0018-9200
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/19764
dc.identifier.url	http://dx.doi.org/10.1109/JSSC.2011.2159056
dc.source.beginpage	2416
dc.source.endpage	2430
dc.source.issue	10
dc.source.journal	IEEE Journal of Solid-State Circuits
dc.source.volume	46
dc.title	A 4.4 pJ/access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy
dc.type	Journal article
dspace.entity.type	Publication
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