Publication:

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application

 
dc.contributor.authorRao, Siddharth
dc.contributor.authorKim, Woojin
dc.contributor.authorVan Beek, Simon
dc.contributor.authorKundu, Shreya
dc.contributor.authorPerumkunnil, Manu
dc.contributor.authorCosemans, Stefan
dc.contributor.authorYasin, Farrukh
dc.contributor.authorCouet, Sebastien
dc.contributor.authorCarpenter, Robert
dc.contributor.authorO'Sullivan, Barry
dc.contributor.authorHoushmand Sharifi, Shamin
dc.contributor.authorJossart, Nico
dc.contributor.authorSouriau, Laurent
dc.contributor.authorGoux, Ludovic
dc.contributor.authorCrotti, Davide
dc.contributor.authorKar, Gouri Sankar
dc.contributor.imecauthorRao, S.
dc.contributor.imecauthorKim, W.
dc.contributor.imecauthorvan Beek, S.
dc.contributor.imecauthorKundu, S.
dc.contributor.imecauthorPerumkunnil, M.
dc.contributor.imecauthorCosemans, S.
dc.contributor.imecauthorYasin, F.
dc.contributor.imecauthorCouet, S.
dc.contributor.imecauthorCarpenter, R.
dc.contributor.imecauthorO'Sullivan, B. J.
dc.contributor.imecauthorSharifi, S. H.
dc.contributor.imecauthorJossart, N.
dc.contributor.imecauthorSouriau, L.
dc.contributor.imecauthorGoux, L.
dc.contributor.imecauthorCrotti, D.
dc.contributor.imecauthorKar, G. S.
dc.contributor.imecauthorRao, Siddharth
dc.contributor.imecauthorKim, Woojin
dc.contributor.imecauthorVan Beek, Simon
dc.contributor.imecauthorKundu, Shreya
dc.contributor.orcidimecRao, Siddharth::0000-0001-6161-3052
dc.contributor.orcidimecVan Beek, Simon::0000-0002-2499-4172
dc.contributor.orcidimecYasin, Farrukh::0000-0002-7295-0254
dc.contributor.orcidimecCouet, Sebastien::0000-0001-6436-9593
dc.contributor.orcidimecCarpenter, Robert::0000-0003-0101-5952
dc.contributor.orcidimecO'Sullivan, Barry::0000-0002-9036-8241
dc.contributor.orcidimecSouriau, Laurent::0000-0002-5138-5938
dc.contributor.orcidimecGoux, Ludovic::0000-0002-1276-2278
dc.date.accessioned2021-11-25T16:43:24Z
dc.date.available2021-11-02T15:58:18Z
dc.date.available2021-11-25T16:43:24Z
dc.date.issued2021
dc.identifier.doi10.1109/IMW51353.2021.9439592
dc.identifier.eisbn978-1-7281-8517-0
dc.identifier.issn2330-7978
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/37675
dc.publisherIEEE
dc.source.beginpage80
dc.source.conferenceIEEE International Memory Workshop (IMW)
dc.source.conferencedateMAY 16-19, 2021
dc.source.conferencelocationDresden, Germany
dc.source.endpage83
dc.source.journalna
dc.source.numberofpages4
dc.title

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application

dc.typeProceedings paper
dspace.entity.typePublication
Files
Publication available in collections: