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Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow
Publication:
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow
Date
2020
Proceedings Paper
https://doi.org/10.1109/VLSI-SOC46417.2020.9344089
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Giacomin, Edouard
;
Boemmels, Juergen
;
Ryckaert, Julien
;
Catthoor, Francky
;
Gaillardon, Pierre-Emmanuel
Journal
na
Abstract
Description
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1791
since deposited on 2021-11-02
395
item.page.metrics.field.last-week
Acq. date: 2025-10-25
Citations
Metrics
Views
1791
since deposited on 2021-11-02
395
item.page.metrics.field.last-week
Acq. date: 2025-10-25
Citations