Publication:

Electrical test demonstration for 0.55 NA EUV single patterning damascene process

Date

2025
Proceedings Paper
https://doi.org/10.1109/IITC66087.2025.11075462
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dc.contributor.authorLariviere, Stephane
dc.contributor.authorBlanco, Victor
dc.contributor.authorVandersmissen, Kevin
dc.contributor.authorDe Wachter, Bart
dc.contributor.authorSangghaleh, Mahtab
dc.contributor.authorNafus, K.
dc.contributor.authorFeurprier, Y.
dc.contributor.authorWako, Y.
dc.contributor.authorFukui, N.
dc.contributor.authorDe Poortere, E. P.
dc.contributor.authorYao, C-H.
dc.contributor.authorHsu, A.
dc.contributor.authorTabery, C.
dc.contributor.authorDoise, J.
dc.contributor.authorDe Schepper, P.
dc.contributor.authorGuzman, N.
dc.date.accessioned2026-03-19T10:10:19Z
dc.date.available2026-03-19T10:10:19Z
dc.date.createdwos2025-10-18
dc.date.issued2025
dc.description.abstractThis work presents the development of a single-layer damascene short loop process to evaluate the patterning performance of single-exposure 0.55 NA lithography. Electrical readouts of up to 3cm long meander and fork structures are used to assess yield across various pitch dimensions. Preliminary results demonstrate successful combo yield for pitches from 32nm to 20nm.
dc.identifier.doi10.1109/IITC66087.2025.11075462
dc.identifier.isbn979-8-3315-3782-1
dc.identifier.issn2380-632X
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/58873
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.beginpageN/A
dc.source.conferenceIEEE International Interconnect Technology Conference (IITC)
dc.source.conferencedate2025-06-02
dc.source.conferencelocationBusan
dc.source.journal2025 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, IITC
dc.source.numberofpages3
dc.title

Electrical test demonstration for 0.55 NA EUV single patterning damascene process

dc.typeProceedings paper
dspace.entity.typePublication
imec.identified.statusLibrary
imec.internal.crawledAt2025-10-22
imec.internal.sourcecrawler
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