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DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks
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DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks
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Date
2012-11
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Deutsch, Sergej
;
Keller, Brion
;
Chickermane, Vivek
;
Mukherjee, Subhasish
;
Sood, Navdeep
;
Goel, Sandeep K.
;
Chen, Ji-Jan
;
Mehta, Ashok
;
Lee, Frank
;
Marinissen, Erik Jan
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Views
1916
since deposited on 2021-10-20
1
last month
1
last week
Acq. date: 2025-12-12
Citations