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Impact of gate-level clustering on automated system partitioning of 3D-ICs

 
dc.contributor.authorDelhaye, Quentin
dc.contributor.authorBeyne, Eric
dc.contributor.authorGoossens, Joel
dc.contributor.authorvan der Plas, Geert
dc.contributor.authorMilojevic, Dragomir
dc.contributor.imecauthorBeyne, Eric
dc.contributor.imecauthorvan der Plas, Geert
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.date.accessioned2023-10-11T10:10:30Z
dc.date.available2023-09-11T17:27:19Z
dc.date.available2023-10-11T10:10:30Z
dc.date.issued2023
dc.identifier.doi10.1016/j.mejo.2023.105896
dc.identifier.issn0026-2692
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/42521
dc.publisherELSEVIER SCI LTD
dc.source.beginpageArt. 105896
dc.source.endpagena
dc.source.issueSeptember
dc.source.journalMICROELECTRONICS JOURNAL
dc.source.numberofpages7
dc.source.volume139
dc.title

Impact of gate-level clustering on automated system partitioning of 3D-ICs

dc.typeJournal article
dspace.entity.typePublication
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