FSD Challenges in 300nm Si Substrate of DTCO/STCO Scaling Options

Abstract

In the design-technology co-optimization (DTCO) and system-technology co-optimization (STCO) scaling era, sub-μm Si substrate has been inevitable for the decent vertical connections. This work, for the first time, evaluates the ESD performance of various ESD devices, including ESD diodes and MOSFET-based ESD devices, with extremely thinned wafer thickness of 300nm and double-sided connectivity. The detriment of the wafer thinning has been assessed for these ESD devices with different key design parameters. Furthermore, the thermal dissipation of these ESD devices with active back-side (BS) contact and metals has been investigated for a possible solution to the thermal issue resulting from the extremely thinned Si substrate.