Lithographic strategies for 0.35µm poly gates for random logic applications

dc.contributor.author	Op de Beeck, Maaike
dc.contributor.author	Van Driessche, Veerle
dc.contributor.author	Van den hove, Luc
dc.contributor.author	Dijkstra, H.
dc.contributor.imecauthor	Op de Beeck, Maaike
dc.contributor.imecauthor	Van Driessche, Veerle
dc.contributor.imecauthor	Van den hove, Luc
dc.contributor.orcidimec	Op de Beeck, Maaike::0000-0002-2700-6432
dc.date.accessioned	2021-09-29T12:45:08Z
dc.date.available	2021-09-29T12:45:08Z
dc.date.embargo	9999-12-31
dc.date.issued	1994
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/289
dc.source.beginpage	407
dc.source.conference	Advances in Resist Technology and Processing XI
dc.source.conferencedate	28/02/1994
dc.source.conferencelocation	San Jose, CA USA
dc.source.endpage	421
dc.title	Lithographic strategies for 0.35µm poly gates for random logic applications
dc.type	Proceedings paper
dspace.entity.type	Publication
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