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An Efficient Embryonic Hardware Architecture based on Network-on-Chip

 
dc.contributor.authorKhalil, Kasem
dc.contributor.authorEldash, Omar
dc.contributor.authorDey, Bappaditya
dc.contributor.authorKumar, Ashok
dc.contributor.authorBayoumi, Magdy
dc.contributor.imecauthorDey, Bappaditya
dc.contributor.orcidimecDey, Bappaditya::0000-0002-0886-137X
dc.date.accessioned2022-07-08T10:09:18Z
dc.date.available2022-05-12T02:18:55Z
dc.date.available2022-07-08T09:20:33Z
dc.date.available2022-07-08T10:09:18Z
dc.date.issued2021
dc.identifier.doi10.1109/MWSCAS47672.2021.9531774
dc.identifier.eisbn978-1-6654-2461-5
dc.identifier.issn1548-3746
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/39811
dc.publisherIEEE
dc.source.beginpage449
dc.source.conferenceIEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
dc.source.conferencedateAUG 09-11, 2021
dc.source.conferencelocationLansing, MI, USA
dc.source.endpage452
dc.source.journalna
dc.source.numberofpages4
dc.title

An Efficient Embryonic Hardware Architecture based on Network-on-Chip

dc.typeProceedings paper
dspace.entity.typePublication
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