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Application of 3D X-Ray Microscopy for 3D IC Process Development

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cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0003-3822-5953
cris.virtualsource.department99f46578-0b77-4a3f-b8e5-a6879cd2ea9a
cris.virtualsource.orcid99f46578-0b77-4a3f-b8e5-a6879cd2ea9a
dc.contributor.authorWang, Teng
dc.contributor.authorDe Wolf, Ingrid
dc.contributor.authorGu, Allen
dc.contributor.authorEstrada, Raleigh
dc.contributor.authorKelly, Steve
dc.date.accessioned2026-10-29T13:34:52Z
dc.date.available2026-10-29T13:34:52Z
dc.date.issued2016
dc.description.abstractABSTRACT 3D X-ray microscopy (XRM) is used to image both 2-layer and multi-layer 3D stacked chips, assembled by both chip-to-chip and chip-to-wafer formats. XRM is able to generate 3D volumetric views and 2D virtual cross-sectional images of interconnects, such as through-silicon vias (TSVs) and micro bump joints in multi-layer 3D stacks. A voxel size down to 0.3 μm is obtained, sufficient to reveal details and defects in highly complicated 3D ICs. XRM offers an effective and versatile non-destructive method for process accuracy metrology, process quality inspection, and failure analysis. In addition, XRM has shown the capability to image chip stacks at different locations on a 300 mm wafer without substantial loss of resolution.
dc.identifier.doi10.37665/waqtgod64202
dc.identifier.issn3067-9052
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60660
dc.language.isoen
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherSMTA
dc.source.conference13th Wafer-Level Packaging Symposium
dc.source.conferencedate2016-10-18
dc.source.conferencelocationSan Jose
dc.source.journal13th Wafer-Level Packaging Symposium
dc.title

Application of 3D X-Ray Microscopy for 3D IC Process Development

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2025-12-02
imec.internal.sourcecrawler
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